This invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device with contact holes differing in depth and a manufacturing method thereof.
As the elements of semiconductor devices have been getting smaller and smaller in these years, multilayer interconnections have been needed for the devices. In this move, device surface planarization is getting important and process techniques, such as CMP (Chemical Mechanical Polishing), are in wide use. The CMP can remove steps at the device surface and planarize the surface. This helps improve the margin of the process in using lithography techniques or etching techniques, so the CMP is becoming indispensable to the miniaturization of semiconductor devices.
With the devices getting smaller, via holes for connecting the upper-layer interconnections to the lower-layer interconnections and contact holes for connecting interconnections to gate interconnections or impurity diffused layers have begun to be filled with suitable material, such as tungsten.
When the planarization techniques and filling techniques are used, the formation of the via holes on the lower-layer interconnections and the upper-layer interconnections is easy in the process of forming multilayer interconnections, because the surface of the insulating film is flat. At the time of the formation of the lower-layer interconnections, however, there will be an adverse effect because the formation of the lower-layer interconnections will be affected seriously by the steps located under them.
With conventional semiconductor manufacturing techniques, the surface of the insulating film was not subjected to the planarization process, with the result that the contact holes were made with the steps remaining at the surface. Since the thickness of the insulating film was almost the same in various places on the film, the depth of the contact holes made in various places on the insulating film was almost the same. As a result, it was easy to fill these contact holes with conductive material. With the introduction of the planarization of insulating films as a result of advances in the miniaturization of semiconductor elements, however, when the contact holes with different depths made in the planarized insulating films are filled with conductive material, various difficulties will arise.
Here, explanation will be given of a case where a semiconductor device with contact holes differing in depth is formed at an insulating film having portions differing in thickness. At the surface of a semiconductor substrate, element-isolating regions, MOS transistors, and the like are formed. The MOS transistors have impurity diffused layers serving as source and drain regions and gate electrodes formed via gate oxide films. The gate electrodes are connected to the gate interconnections, which are also arranged on the element-isolating regions. These element-isolating regions and other related portions form the steps.
Next, on the semiconductor substrate, an insulating film made of, for example, SiO.sub.2, is formed by CVD techniques and the steps produced at the surface of the insulating surface are planarized by the CMP. In the insulating film, the thickness on the impurity diffused layer is greater than that on the element-isolating region. In the planarized insulating film, contact holes for exposing part of the impurity diffused layer and contact holes for exposing part of the gate interconnections on the element-isolating regions are made. The depth of the contact hole for exposing the impurity diffused layer is greater than that of the contact hole for exposing the gate interconnection on the element-isolating region. Thereafter, inside the deep contact holes and shallow contact holes, a conductive material made of, for example, tungsten, is grown to form contacts in the individual holes.
However, it was difficult to fill each of the deep contact holes and shallow contact holes with a tungsten film. Specifically, when the growth rate of the tungsten film is adjusted to the shallow contact holes so that the tungsten film may grow sufficiently in the shallow contact holes, the growth of the tungsten film in the deep contact holes is insufficient, contributing to disconnections in a later process of forming interconnections.
To prevent this, the growth rate of the tungsten film is adjusted to the deep contact holes so that the deep contact holes may be filled sufficiently with a tungsten film. In this case, however, the tungsten overgrows in the shallow holes. The overgrown tungsten film overflows the shallow contact holes. The overflowed tungsten contributes to the short-circuiting of interconnections.
The short-circuited interconnections lead to a drop in the yield. Even when the overflowed tungsten causes no short circuit, it contributes to a decrease in the reliability.
FIG. 5 shows the relationship between the distance between the deep contact holes and the shallow contact holes and the yield for the short-circuiting of interconnections.
FIG. 5 shows a case where the depth of the deep contact holes is assumed to be, for example, 12000 angstroms, the depth of the shallow contact holes is assumed to be, for example, 6300 angstroms, and the diameter of both contact holes is assumed to be from 0.45 to 0.65 .mu.m.
As seen from the figure, the yield decreases when the distance between both of the contact holes is 0.5 .mu.m or less. Specifically, with the above-described dimensions, whether the deep contact holes and shallow contact holes are arranged with a distance of 0.55 .mu.m between them, there is much danger that they will be short-circuited with each other.
As described earlier, it has been difficult to fill contact holes differing in depth suitably with conductive material at the same time.